How can I implement hierarchical partial reconfiguration on the Intel Arria 10 SoC Development Board? (intel Hierarchical Partial Reconfiguration Design Arria 10 SoC Development Board User Guide)

Answer

manuals.plus

Mar 26, 2025 - 08:58 AM

To implement hierarchical partial reconfiguration on the Intel Arria 10 SoC Development Board, you can follow the steps outlined in the "Hierarchical Partial Reconfiguration Tutorial for Intel Arria 10 SoC Development Board" user guide provided by Intel.

Here is a summary of the steps involved:

1. Getting Started: Set up your working environment and compile the flat design.
2. Create a Child Level Sub-module: Create a child sub-module that is nested within the parent sub-module.
3. Creating Design Partitions: Create design partitions for each PR region that you want to partially reconfigure.
4. Allocating Placement and Routing Region for PR Partitions: Allocate placement and routing regions for the PR partitions in the device floorplan.
5. Adding the Intel Arria 10 Partial Reconfiguration Controller IP Core: Add the Intel Arria 10 Partial Reconfiguration Controller IP core to your project.
6. Defining Personas: Define personas for the parent and child PR partitions.
7. Creating Revisions: Create synthesis and implementation revisions for each persona.
8. Generating the Hierarchical Partial Reconfiguration Flow Script: Generate a flow script that automates the PR design flow.
9. Running the Hierarchical Partial Reconfiguration Flow Script: Run the flow script to synthesize and implement the personas.
10. Programming the Board: Program the resulting RBF files into the FPGA on the Intel Arria 10 SoC Development Board.

For detailed instructions and examples, please refer to the "Hierarchical Partial Reconfiguration Tutorial for Intel Arria 10 SoC Development Board" user guide provided by Intel.