User Manual Q&AAnswer
Mar 07, 2025 - 03:29 AM
To parameterize the Intel Cyclone 10 Native Floating-Point DSP FPGA IP, follow these steps:
1. Open Intel Quartus Prime Pro Edition and create a new project targeting an Intel Cyclone 10 GX device.
2. In the IP Catalog, navigate to Library ➤ DSP ➤ Primitive DSP ➤ Intel Cyclone 10 GX Native Floating Point DSP.
3. The Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP parameter editor will open.
4. In the New IP Variation dialog box, enter an Entity Name and click OK.
5. Under Parameters, select the DSP Template and the View you want for your IP core.
6. In the DSP Block View, toggle the clock or reset of each valid register.
7. For Multiply Add or Vector Mode 1, click on the Chain In multiplexer in the GUI to select input from the chainin port or Ax port.
8. Click the Adder symbol in the GUI to select addition or subtraction.
9. Click on the Chain Out multiplexer in the GUI to enable the chainout port.
10. Click Generate HDL.
11. Click Finish.
By following these steps, you can parameterize the Intel Cyclone 10 Native Floating-Point DSP FPGA IP according to your design requirements. For more detailed information, refer to the Intel Cyclone 10 Native FloatingPoint DSP FPGA IP User Guide.
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