How do I configure the IOPLL IP core in the Intel Quartus Prime Design Suite? (intel IOPLL FPGA IP Core User Guide)

Answer

manuals.plus

Mar 07, 2025 - 03:23 AM

To configure the IOPLL IP core in the Intel Quartus Prime Design Suite, you need to follow these steps:

1. Open the IP Catalog in the Intel Quartus Prime Design Suite.
2. Locate the IOPLL IP core in the PLL category.
3. Set the parameters for the IOPLL IP core according to your requirements. The parameters include device family, speed grade, PLL mode, reference clock frequency, operation mode, number of clocks, desired frequency, phase shift, duty cycle, and more. Refer to the IOPLL IP Core Parameters section in the user guide for detailed information about each parameter.
4. Configure the settings tab, which includes options for PLL bandwidth preset, PLL auto reset, second reference clock frequency, active clock signal, clock bad signal, switchover mode, and switchover delay.
5. Configure the cascading tab if you want to cascade multiple PLLs. This tab includes options for creating a cascade out signal, selecting the cascading source, and creating an adjpllin or cclk signal.
6. Configure the dynamic reconfiguration tab if you want to enable dynamic reconfiguration of the PLL. This tab includes options for enabling dynamic reconfiguration, enabling access to dynamic phase shift ports, MIF generation option, path to new MIF file, path to existing MIF file, and more.
7. Configure the advanced parameters tab if you want to view the physical PLL settings that will be implemented based on your input.
8. Connect the required input and output ports of the IOPLL IP core, such as refclk, rst, fbclk, fboutclk, zdbfbclk, locked, refclk1, extswitch, activeclk, clkbad, cascade_out, and outclk[].
9. Generate the HDL code for the IOPLL IP core and integrate it into your design.

For more detailed information and step-by-step instructions, refer to the "IOPLL Intel FPGA IP Core User Guide" provided by Intel.