User Manual Q&AAnswer
Mar 07, 2025 - 03:21 AM
The 4G Turbo-V Intel FPGA IP is a forward-error correction (FEC) channel code that improves the energy efficiency of wireless communication systems. It is suitable for 3G and 4G mobile communications, such as UMTS and LTE, as well as satellite communications. The IP includes a downlink accelerator and an uplink accelerator.
The downlink accelerator adds redundancy to the data in the form of parity information. It includes a code block cyclic redundancy code (CRC) attachment, a Turbo encoder, and a Turbo rate matcher with subblock interleaver, bit collector, bit selector, and bit pruner.
The uplink accelerator exploits redundancy to correct a reasonable number of channel errors. It includes a subblock deinterleaver and a Turbo decoder with CRC check.
To use the 4G Turbo-V IP, you can generate a downlink or uplink accelerator using the Intel Quartus Prime Pro software. The IP supports different device families, including Intel Agilex, Intel Arria 10, and Intel Stratix 10.
For more detailed information on the functionality, timing diagrams, and interfaces of the 4G Turbo-V Intel FPGA IP, please refer to the Intel 4G Turbo-V FPGA IP User Guide.
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