User Manual Q&AAnswer
Mar 07, 2025 - 03:13 AM
To simulate an Intel Quartus Prime Pro Edition design using ModelSim - Intel FPGA Edition, follow these steps:
1. Open the Example Design: Download and unzip the Quartus_Pro_PLL_RAM.zip design example. Launch the Intel Quartus Prime Pro Edition software and open the pll_ram.qpf project file.
2. Specify EDA Tool Settings: In the Intel Quartus Prime software, click Assignments ➤ Settings ➤ EDA Tool Settings. Under Simulation, select ModelSim-Intel FPGA as the Tool name.
3. Generate a Simulator Setup Script Template: Click Processing ➤ Start Compilation to compile the design. Then, click Tools ➤ Generate Simulator Setup Script for IP. Retain the default settings for the setup script file.
4. Modify the Simulator Setup Script: Open the msim_setup.tcl file in a text editor. Create a new text file named mentor_example.do in the /PLL_RAM/mentor/ directory. Copy the code enclosed within the TOP-LEVEL TEMPLATE – BEGIN and TOP-LEVEL TEMPLATE – END comments from msim_setup.tcl and paste it into mentor_example.do. Uncomment the highlighted simulation commands in mentor_example.do.
5. Compile and Simulate the Design: Launch the ModelSim - Intel FPGA Edition software. Open the testbench_1.v file and mentor/mentor_example.do file. In the Transcript window, type "do mentor_example.do" and press Enter.
6. View Signal Waveforms: Click the Wave window to view the simulation waveform. To view the signals in the top-level pll_ram.v design, click the Sim tab. Expand the tb folder in the Objects tab to view the module signals. Click a module under Test1 to display its signals in the Objects window. The Library window displays the simulation library files.
7. Add Signals to the Simulation: In the Objects window, locate the UP_module, DOWN_module, PLL_module, and RAM_module modules. Select RAM_module and add internal signals by right-clicking rdaddress and wraddress, then clicking Add Wave. Alternatively, drag and drop these signals from the Objects window to the Wave window. Click Simulate ➤ Run ➤ Continue to generate waveforms for the new signals.
8. Rerun Simulation: If you make changes to the simulation setup or testbench_1.v file, click Simulate ➤ Restart. Then, click Simulate ➤ Run ➤ Run -all to rerun the simulation.
9. Modify the Simulation Testbench: Open the testbench_1.v file in the ModelSim - Intel FPGA Edition simulator. Edit the testbench parameters and save the file. Click Simulate ➤ Restart to generate waveforms for the modified testbench. Click Simulate ➤ Run ➤ Run -all to simulate according to the new testbench specifications.
Please note that these instructions are a summary of the steps provided in the Intel UG-20093 ModelSim FPGA Edition Simulation User Guide. For more detailed information and screenshots, refer to the user guide.
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