What is Scalable Switch Intel for PCI Express configuration for embedded endpoints instead of downstream ports? (Scalable Switch intel FPGA IP PCI Express User Guide)

Answer

manuals.plus

Mar 07, 2025 - 03:08 AM


To configure the Scalable Switch Intel FPGA IP for PCI Express to support embedded endpoints instead of discrete downstream ports, you can use the Intel P-Tile Avalon Streaming IP for PCI Express in TLP Bypass mode. This allows you to utilize fewer PCIe physical links.



Here are the steps to configure the embedded endpoints using the Scalable Switch Intel FPGA IP:



1. Ensure that you have the Intel Quartus Prime Design Suite version 20.4 or later installed.



2. Connect the Scalable Switch Intel FPGA IP to the Intel P-Tile Avalon Streaming IP for PCI Express in TLP Bypass mode.



3. In the Intel Quartus Prime software, open your project and go to the IP Catalog.



4. Locate the Scalable Switch Intel FPGA IP for PCI Express and double-click on it to open the IP Parameter Editor.



5. In the IP Parameter Editor, select the "Embedded Endpoint Mode" option.



6. Configure the desired number of embedded endpoints and their associated settings, such as address mapping and interrupt handling.



7. Save the configuration and generate the IP core.



8. Instantiate the generated IP core in your design and connect it to the desired components.



By following these steps, you can configure the Scalable Switch Intel FPGA IP for PCI Express to support embedded endpoints, allowing you to optimize the usage of PCIe physical links. For more detailed information and specific settings, refer to the "Scalable Switch Intel FPGA IP for PCI Express User Guide" provided by Intel.