How to create Low Latency E-Tile 40G Ethernet Intel FPGA IP core hardware design and testbench? (Low Latency E-Tile 40G Ethernet intel FPGA IP Design User Guide)

Answer

manuals.plus

Mar 07, 2025 - 03:05 AM

To generate the hardware design example and testbench for the Low Latency E-Tile 40G Ethernet Intel FPGA IP core, follow these steps:

1. Open the Intel Quartus Prime Pro Edition software and create a new project or open an existing project.
2. In the IP Catalog, select the Low Latency E-Tile 40G Ethernet Intel FPGA IP.
3. Specify a top-level name for your custom IP variation and click OK.
4. In the IP parameter editor, specify the parameters for your IP core variation. Note that there are certain parameters that should not be enabled or set to specific values for correct simulation and functionality.
5. On the Example Design tab, enable the Simulation option to generate the testbench and select the Synthesis option to generate the compilation-only and hardware design examples.
6. Under Target Development Kit, select the appropriate development kit for your device (Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit or Agilex F-series Transceiver-SoC Development Kit).
7. Click the Generate Example Design button and specify the directory path and name for the design example.
8. Once the design example is generated, you can simulate it using the supported simulator of your choice by running the simulation script provided in the example testbench directory.
9. To compile and configure the design example on hardware, launch the Intel Quartus Prime Pro Edition software and select Processing ➤ Start Compilation. Then, follow the steps in the Programmer tool to program the hardware design example on your Intel device.

Please refer to the "Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example User Guide" for more detailed information and step-by-step instructions on generating and testing the hardware design example.