User Manual Q&AAnswer
Mar 07, 2025 - 02:46 AM
To generate the hardware design example for the Intel 50G Ethernet IP core, you need to follow these steps:
1. Open the Intel Quartus Prime software and create a new project or open an existing project.
2. In the IP Catalog, select the 50G Ethernet IP core.
3. Specify a top-level name for your IP variation and click OK.
4. The parameter editor will add the top-level .qsys (or .ip) file to the project automatically.
5. On the IP tab, specify the parameters for your IP core variation.
6. On the Example Design tab, select the Synthesis option to generate the hardware design example.
7. Select the Arria 10 GX Transceiver Signal Integrity Development Kit as the Hardware Board.
8. Click the Generate Example Design button.
9. Specify the directory path and name for the design example directory.
10. Click OK to generate the hardware design example.
Please note that this design example targets the Arria 10 GT device and requires a 25G retimer. It is recommended to contact your Intel FPGA representative to inquire about a suitable platform to run this hardware example.
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