User Manual Q&AAnswer
Mar 07, 2025 - 02:22 AM
To generate the F-Tile CPRI PHY Intel FPGA IP hardware design example and testbench, follow these steps:
1. Open the Intel Quartus Prime Pro Edition software.
2. In the IP Catalog, locate and select the F-Tile CPRI PHY Intel FPGA IP.
3. The New IP Variation window will appear. Specify a top-level name for your custom IP variation and click OK.
4. The parameter editor will appear. On the IP tab, specify the parameters for your IP core variation.
5. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
6. On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL.
7. Click the Generate Example Design button. The Select Example Design Directory window will appear.
8. If you want to modify the design example directory path or name, browse to the new path and type the new design example directory name.
9. Click OK to generate the design example.
The generated design example files will be organized in a directory structure, as described in the manual. The directory will contain testbench files for simulation and hardware design files for compilation and configuration on the FPGA device.7
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