How do I implement a Bus LVDS interface in supported Intel FPGA device families? (intel AN 522 Implementing Bus FPGA Device Families User Guide)

Answer

manuals.plus

Mar 04, 2025 - 12:45 AM

To implement a Bus LVDS interface in supported Intel FPGA device families, you will need to follow the guidelines provided in the "Implementing Bus LVDS Interface in Supported Intel FPGA Device Families" user guide. This guide provides information on the supported FPGA device families, I/O standards, and design considerations for implementing a Bus LVDS interface.

First, you need to select the appropriate FPGA device family based on your requirements. The guide lists the supported device families, including Stratix, Arria, Cyclone, and MAX 10.

Next, you need to choose the correct I/O standard for your application. The guide provides a table that lists the supported I/O standards for each device family. You should select the I/O standard that matches your specific requirements, such as differential SSTL-18 Class I or Class II, or differential SSTL-2 Class I or Class II.

Once you have selected the device family and I/O standard, you can proceed with the design implementation. The guide provides design considerations, such as bus termination, stub length, and driver slew rate, that you should take into account to ensure optimal signal integrity and performance.

Additionally, the guide includes a design example that demonstrates how to instantiate the BLVDS I/O buffer in the supported devices using the relevant GPIO IP cores or ALTIOBUF IP core. The design example guidelines provide step-by-step instructions for each supported device family.

For more detailed information and instructions, please refer to the "Implementing Bus LVDS Interface in Supported Intel FPGA Device Families" user guide.