How do I read the unique chip ID for Intel FPGA devices using the Chip ID FPGA IP Cores? (intel Chip ID FPGA IP Cores User Guide)

Answer

manuals.plus

Mar 03, 2025 - 03:05 AM

To read the unique chip ID for Intel FPGA devices using the Chip ID FPGA IP Cores, you need to follow these steps:

1. Instantiate the appropriate Chip ID IP core for your FPGA device. The supported devices and corresponding IP cores are listed in the user guide.

2. Connect the clkin input port of the IP core to a clock signal. The maximum supported frequency varies depending on the FPGA device.

3. Connect the reset input port of the IP core to a synchronous reset signal. To reset the IP core, assert the reset signal high for at least 10 clkin cycles.

4. Drive the readid input port of the IP core to initiate the read ID operation. To start the read ID operation, drive the readid signal high for at least 3 clock cycles, then pull it low. The IP core will start reading the value of the chip ID.

5. Monitor the data_valid output port of the IP core. When the signal is low, the IP core is in the initial state or in progress to load data from a fuse ID. After the IP core asserts the signal, the data is ready for retrieval.

6. Retrieve the unique chip ID from the chip_id output port of the IP core. The chip_id[63:0] output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.

Note: The Chip ID IP cores do not have simulation model files. To validate these IP cores, it is recommended to perform hardware evaluation.

For more detailed information and specific guidelines for each supported FPGA device, please refer to the "Chip ID FPGA IP Cores User Guide" provided by Intel.