User Manual Q&AAnswer
Mar 02, 2025 - 08:18 AM
To migrate from control block-based devices to SDM-based devices for flash access and remote system update, you can follow the guidelines provided in the "Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices" user guide. Here are the steps you can take:
1. Control Block-Based Devices (Intel Arria 10 and V-Series Devices):
- Use the Generic Serial Flash Interface Intel FPGA IP and QUAD Serial Peripheral Interface (SPI) Controller II for flash access.
- Use the Remote Update Intel FPGA IP for remote system update.
- Connect the flash devices to either dedicated Active Serial (AS) pins or general purpose I/O (GPIO) pins.
- If using QSPI flash devices for FPGA configuration and user data storage, connect them to the dedicated ASMI pin.
2. SDM-Based Devices (Intel Stratix 10 and Intel Agilex Devices):
- Use the Mailbox Client Intel FPGA IP for both flash access and remote system update.
- Connect the configuration flash to the SDM I/O pins.
- Commands and/or configuration images are sent to the host controller, which translates them into Avalon memory-mapped format and sends them to the Mailbox Client Intel FPGA IP.
- The Mailbox Client Intel FPGA IP drives the commands/data and receives responses from the SDM.
- The SDM writes the configuration images to the QSPI flash device.
3. Comparison between Serial Flash Mailbox, Mailbox Client, and Mailbox Client with Avalon Streaming Interface Intel FPGA IPs:
- The Mailbox Client with Avalon Streaming Interface Intel FPGA IP is recommended for Intel Agilex devices and supports Avalon streaming interface for faster data streaming.
- The Serial Flash Mailbox Client Intel FPGA IP is only supported in Intel Stratix 10 devices and uses Avalon memory-mapped interface.
- The Mailbox Client Intel FPGA IP is recommended for both Intel Stratix 10 and Intel Agilex devices and uses Avalon memory-mapped interface.
4. Using GPIO as Interface for Accessing Flash Devices:
- In some cases, the QSPI flash device can be connected to GPIO pins in the FPGA for general purpose memory storage.
- The Generic Serial Flash Interface Intel FPGA IP can be used to access the flash device connected to GPIO pins.
- In Intel Stratix 10 and Intel Agilex devices, the parameter setting "enable SPI pin interface" must be enabled in the Generic Serial Flash Interface Intel FPGA IP to prevent errors during compilation.
- For configuration purposes, connect the flash devices to the SDM I/O pins.
For more detailed information and instructions, refer to the "Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices" user guide provided by Intel.
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