User Manual Q&AAnswer
Mar 02, 2025 - 08:09 AM
The Intel Erasure Decoder Reference Design is a Reed-Solomon decoder that specifically focuses on correcting erasures rather than errors. It uses a nonbinary, cyclic, linear block error correction code. The design algorithm and architecture are different from a traditional Reed-Solomon decoder as it avoids the complexity of finding error locations.
The Erasure Decoder works by trying to fill up the input with p=n-k symbols to form a valid codeword, by fulfilling the parity equations. It uses a parity matrix and a generator matrix to define the parity equations. The design only works with small Reed-Solomon codes, such as RS(14,10), RS(16,12), RS(12,8), or RS(10,6).
The erasure pattern, represented by the n-bits wide in_era input, addresses the ROM where the design stores parity submatrices. The design uses an address compression module to handle the limited number of possible erasure patterns.
The Erasure Decoder can receive symbols at its input at any rate, up to the total block length n per cycle for maximum throughput. You can configure the number of channels and parallelism to process multiple codewords simultaneously. The decoder produces the full decoded codeword, including check symbols, in one cycle.
The Erasure Decoder IP Core has various parameters that can be configured, such as the number of channels, number of bits per symbol, number of symbols per codeword, number of check symbols per codeword, number of parallel symbols per channel, and the field polynomial.
The design interfaces with the Avalon-ST interface, which supports backpressure for flow control. It has clock and reset signals for synchronization, as well as input and output signals for data transfer.
For more detailed information and instructions on using the Intel Erasure Decoder Reference Design, please refer to the provided manual.
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