User Manual Q&AAnswer
Feb 28, 2025 - 09:59 PM
To generate the Intel Arria 10 hardware example design and testbench for the Intel 50G Interlaken IP core, follow these steps:
1. Open the IP Catalog in the Intel Quartus Prime software.
2. Select the Intel Arria 10 target device family.
3. Locate and double-click on the 50G Interlaken IP core.
4. In the New IP Variation window, specify a top-level name for your custom IP variation and select the Intel Arria 10 device.
5. Click OK to open the parameter editor.
6. In the parameter editor, specify the parameters for your IP core variation on the IP tab.
7. On the Example Design tab, select the Simulation option to generate the testbench and select the Synthesis option to generate the hardware example design.
8. Choose Verilog as the Generated HDL Format.
9. Select the Intel Arria 10 GX Transceiver Signal Integrity Development Kit as the Target Development Kit.
10. Click the Generate Example Design button.
Once the example design generation is complete, you can find the hardware configuration, simulation, and test files in the specified directory. You can then simulate the testbench using a supported simulator and compile and test the hardware example design using the Intel Quartus Prime software.
For more detailed information and step-by-step instructions, refer to the "Intel 50G Interlaken Design Example User Guide" provided by Intel.
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