User Manual Q&AAnswer
Feb 24, 2025 - 07:51 AM
To generate the design example and testbench for the F-Tile Interlaken Intel FPGA IP core, follow these steps:
1. Open the Intel Quartus Prime Pro Edition software and create a new project or open an existing project.
2. Select the device family Agilex and choose a device with F-Tile for your design.
3. In the IP Catalog, locate and double-click F-Tile Interlaken Intel FPGA IP to open the New IP Variant window.
4. Specify a top-level name for your custom IP variation and click OK. The parameter editor will appear.
5. In the parameter editor, specify the parameters for your IP core variation on the IP tab.
6. On the Example Design tab, select the Simulation option to generate the testbench.
7. Choose the desired HDL format (Verilog or VHDL) for the generated example design.
8. Click Generate Example Design and select the directory where you want to save the design example.
9. Modify the design example directory path or name if desired and click OK.
10. The design example and testbench files will be generated in the specified directory.
Note: Hardware compilation and testing will be available in the Intel Quartus Prime Pro Edition software version 21.4.
For more detailed instructions and information on hardware and software requirements, please refer to the "F-Tile Interlaken Intel FPGA IP Design Example User Guide" provided with the product.
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