User Manual Q&AAnswer
Jan 16, 2025 - 05:10 AM
The main design changes in the ESPRESSIF ESP32 Chip Revision v3.0 are as follows:
1. PSRAM Cache Bug Fix: This fix addresses a read and write error that could occur when the CPU accesses the external SRAM in a certain sequence. More details about this issue can be found in item 3.9 in the ESP32 Series SoC Errata.
2. Read Error Fix: This fix resolves a read error that could occur when each CPU reads certain different address spaces simultaneously. More details about this issue can be found in item 3.10 in the ESP32 Series SoC Errata.
3. 32.768 KHz Crystal Oscillator Stability Improvement: The stability of the 32.768 KHz crystal oscillator has been optimized to address a low probability issue where it couldn't start properly under chip revision v1.0 hardware.
4. Fault Injection Issues Fix: Fault injection issues related to secure boot and flash encryption have been fixed. This ensures better security. More information can be found in the Security Advisory concerning fault injection and eFuse protections (CVE-2019-17391) and Espressif Security Advisory Concerning Fault Injection and Secure Boot (CVE-2019-15894).
5. TWAI Module Baud Rate Improvement: The minimum baud rate supported by the TWAI module has been changed from 25 kHz to 12.5 kHz, providing more flexibility in communication.
6. Download Boot Mode Disable: The new chip revision allows the Download Boot mode to be permanently disabled by programming a new eFuse bit called UART_DOWNLOAD_DIS. When this bit is set to 1, Download Boot mode cannot be used, and booting will fail if the strapping pins are set for this mode. This bit can be programmed and read through specific registers.
These design changes improve the performance, stability, and security of the ESPRESSIF ESP32 Chip Revision v3.0.
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